The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Typically, with many multi-chip packaging arrangements, a packaging arrangement is arranged in one of either a package-on-package (PoP) arrangement, or a multi-chip module (MCM) arrangement. These packaging arrangements tend to be fairly thick (e.g., approximately 1.7 millimeters to 2.0 millimeters).
A PoP arrangement may include an integrated circuit that combines two or more packages on top of each other. For instance, a PoP arrangement may be configured with two or more memory device packages. A PoP arrangement may also be configured with mixed logic-memory stacking that includes logic in a bottom package and memory in a top package or vice versa.
Typically, a die of associated with a package located on the bottom of a PoP arrangement (referred to herein as a “bottom package”) limits the footprint of a package located above the bottom package (referred to herein as a “top package”) to be a certain size. Additionally, such a configuration generally limits the top package to two rows of peripheral solder balls. An example of such a packaging arrangement 800 is illustrated in FIG. 8 and includes a top package 802 and a bottom package 804. As can be seen, the bottom package 804 includes a die 806 attached to a substrate 808 via an adhesive 810. The die 806 is coupled to the substrate 808 via a wirebonding process with wires 812. Solder balls 814 are provided for coupling the packaging arrangement 800 to another substrate (not illustrated) such as, for example, a printed circuit board (PCB). The top package 802 includes a die 816 coupled to a substrate 818. Solder balls 820 are provided to couple the top package 802 to the bottom package 804. The top package 802 may include an enclosure 822, generally in the form of an encapsulant, if desired. As can be seen, only two rows of solder balls 820 can be provided due to the presence of the die 806 and an enclosure 824 (generally in the form of an encapsulant and which may or may not be included) of the bottom package 804. Thus, top packages may be required to have larger sizes or footprints to avoid the die 806 of bottom packages when a top package is attached to the bottom package. Such packaging arrangements 800 can also present problems with clearance issues for the top package 802 with respect to the die 806 and/or enclosure 824.
FIG. 9 illustrates another example of a packaging arrangement 900 where a bottom package 904 has been created with a Mold-Array-Process (MAP). The bottom package 904 is similar to the bottom package 804 of FIG. 8 and includes an encapsulant 906. The encapsulant 906 is generally etched to expose solder balls 908. Alternatively, the encapsulant 906 is etched and then solder balls 908 are deposited within the openings 910. Such a packaging arrangement 900 once again only allows for the inclusion of two rows of solder balls 820 around the periphery of the top package 802 due to the presence of the die 806 and the encapsulant 906. Such packaging arrangements 900 can also present problems with clearance issues for the top package 802 with respect to the die 806 and the encapsulant 906, as well as alignment issues with respect to the openings 910.